Design and Implementation of EPON Tester Hardware Platform

With the gradual expansion of the commercial scale of Ethernet-based passive optical networks (EPON), interoperability testing between devices of different vendors and engineering acceptance testing and operation and maintenance of EPON systems have become increasingly urgent. For this reason, we have designed and developed the EPON tester. . This article analyzes the functional requirements of the EPON tester, briefly describes the overall framework of the EPON tester, and focuses on the design of the EPON tester hardware platform and the implementation of the field-programmable gate array (FPGA) for its core functions.

Ethernet-based Passive Optical Network (EPON) is an access network technology that combines the advantages of Ethernet and Passive Optical Network (PON). It has large capacity, low cost, good support for IP services, and mature technology and maintenance. The advantages of simplicity are one of the ideal solutions for the future realization of FTTx. At present, EPON systems have been widely applied in Japan, and many EPON systems in China have been put into commercial applications. In order to enable EPONs to be successfully applied on a low-cost and large-scale basis, not only the EPON optical line terminal (OLT) and optical network unit (ONU) devices of different vendors can communicate with each other, but also it is necessary to conveniently and effectively complete the engineering acceptance before the EPON network is opened. In the process of EPON network operation and convenient maintenance. Due to the EPON point-to-multipoint topology and its corresponding uplink TDMA (TDMA) approach, traditional network test equipment cannot directly intervene in the EPON system and can only be correlated through the EPON user-side and network-side interfaces. Because of this test, it is not possible to monitor the internal operating status of EPON and cannot test and analyze the EPON related protocols that affect interoperability. For this purpose, we have designed and developed the EPON tester to help operators conduct equipment interoperability testing before EPON networking and post-network project acceptance and network maintenance.

1. System Introduction EPON adopts single-fiber two-way communication mode. To observe the internal operation of EPON, we connect an X-type optical coupler between the OLT and the optical fiber of the optical distribution network (ODN) to separate part of the uplink and downlink optical signals. EPON tester to achieve the monitoring of uplink and downlink, as shown in Figure 1.

The EPON tester is composed of two parts: the hardware platform and the supporting software console. The hardware platform is responsible for the collection and processing of the EPON protocol frames and related data and the communication with the software console. The software controls the EPON tester. The station is responsible for analysis of EPON related protocols, provision of user interfaces, and configuration management of hardware platforms. This article focuses on the design and implementation of the EPON tester hardware platform.

2. Analysis of hardware platform functional requirements The EPON tester focuses on the EPON reconciliation (RS) sublayer, multipoint MAC control (MPCP) sublayer, and operation management and maintenance (OAM) sublayer that affect EPON interworking and operation and maintenance. The RS sub-layer defines the preamble format of the EPON. It introduces a logical link identifier (LLID) on the basis of the original Ethernet preamble to distinguish the logical connection between the OLT and each ONU, and adds an 8-bit cyclic redundancy to the preamble. CRC8; The MPCP sublayer is responsible for the registration of the ONU to the OLT and the operation of the upstream TDMA mechanism. The OAM sublayer is responsible for the functions of the EPON network operation and maintenance. The EPON reference model is shown in Figure 2.

Figure 2 EPON reference model There are two main functions of the EPON tester: to help discover the cause of influencing interoperability and to facilitate the management and maintenance of the EPON network. The former function mainly means that it can help analyze whether the ONU registration process conforms to the standard, whether the upper layer OAM message interaction and service interoperability exist after the registration is successful, and the latter function mainly means that it can provide an online ONU for network maintenance personnel. The statistics of basic information and link parameters are used to facilitate the operator's management of the network and fault location.

According to the functional requirements of the EPON tester and our functional separation of the EPON tester hardware platform and software console, the functional requirements of the EPON tester hardware platform are determined as follows:

(1) Extract the frames involved in the ONU registration process.

(2) Acquire unregistered process MPCP frames and OAM frames according to the configured filtering conditions. For the characteristics of EPON, the filtering conditions may be LLID, a user-defined 6-byte long keyword in the first 64 bytes of the frame, or an "and/or" combination of the two. Considering the factors such as protocol frame traffic, encapsulation overhead sent to the software console, and the console interface's rate limit and implementation complexity, it supports up to 64 LLID filter conditions, and two sets of user-defined keywords, keyword support Accurate to bit mask configuration.

(3) Put a local clock tag on the collected EPON protocol frame (MPCP/OAM frame) and indicate whether it is from the EPON uplink or downlink.

(4) Error rate statistics of the EPON preamble verification, supporting the configuration of statistical enabling and statistics data reporting periods.

(5) Based on a maximum of 256 LLIDs, statistics on the service traffic and frame check sequence (FCS) check results of the correct preamble EPON frame are supported, and statistics enablement and configuration of the statistical data report period are supported.

(6) The collected EPON protocol frames and statistics are encapsulated into Ethernet frames and sent to the software console for analysis through the Fast Ethernet interface.

(7) The configuration contents of the hardware platform are delivered by the software console through the Fast Ethernet interface. The configuration includes the filtering conditions of the EPON protocol frames, the enabling and reporting of link statistics items, and the EPON protocol frames and statistics encapsulated on the Ethernet. In the frame source address/destination address/type (DA/SA/type) field, etc., the hardware platform should support returning the configuration confirmation frame to the software console.

3. Design and Implementation of Hardware Platform 3.1 Overall Hardware Structure The composition of the EPON tester hardware platform is shown in Figure 3.

Figure 3 EPON tester hardware platform block diagram The optical receiver module uses an EPON optical transceiver module that meets the requirements of the 1000Base-PX optical interface in the IEEE 802.3ah specification, but uses only the optical receiver. The Gigabit Ethernet transceiver chip uses a commercial chip that performs bit synchronization and serial/parallel conversion functions, and then outputs the parallel data to the EPON tester core functional field programmable gate array (FPGA) through a 10-bit interface (TBI). deal with.

The core function FPGA completes the core processing functions of the underlying hardware platform, including the collection of EPON protocol frames, EPON link parameter statistics, and user configuration, and comprehensively considers the resource requirements, scalability, and low-cost requirements of these functions for FPGAs. Altera's stratix series chips.

The 100M physical layer (PHY) chip uses the VT6108S, which implements the interface functions of the core function FPGA and the software console. Since the core function FPGA collects data at a peak rate of up to 1 Gigabit, and the output to the console is only 100 Gigabits, an external static memory (SRAM) is used to buffer the output data.

3.2 FPGA design of the core function 3.2.1 Acquisition of EPON agreement frame Fig. 4 is the acquisition frame diagram of the up/down agreement frame. The Gigabit transceiver chip sends the EPON uplink/downlink data to the core function FPGA through the TBI interface. The FPGA synchronizes the received data to the internal 125 MHz clock of the FPGA in an asynchronous first-in first-out (FIFO) manner, and then performs 8B/. 10B decoding, convert to Gigabit Media Independent Interface (GMII) format data and recover each frame.

Figure 4: Up/down frame acquisition frame After the EPON preamble check and FCS check, the wrong frame will be discarded. Since the type field of the MPCP frame is 0x8808 and the type field of the OAM frame is Ox8809, the frame classification module screens out the MPCP/OAM frame send filter module accordingly.

The filter module includes a registration process extraction module and a user-defined filter module. The registration process extraction module can filter out all the registration process frames according to the LLID and the intra type/opcode field, and send the rest of the frames to the user-defined filter module. The user-defined filter module supports filtering by LLID, or filtering by user-defined intra-field fields, or filtering by the "and/or" combination of the two filtering conditions. For the specific parameters, see the hardware platform functional requirements analysis.

Because the interface between the hardware platform and the software console is a 100M Ethernet interface, the collected EPON protocol frame (including the EPON preamble) needs to be encapsulated into an Ethernet frame and then output to the software console. The EPON protocol should be reflected as much as possible during encapsulation. Original frame information, such as the acquisition time, EPON uplink direction, or downlink direction. These are identified in the timestamp field and the flag field. The length of the EPON frame encapsulated into the Ethernet frame may exceed the maximum transmission of the Ethernet. A unit (MTU), an EPON protocol frame having a length greater than 1490 bytes, is divided into two-stage encapsulation, and information on fragmentation is also contained in the flag field. The package format is shown in Figure 5. In the subtype field, the payload part of the Ethernet frame is the EPON protocol frame.

Figure 5 Encapsulation of EPON protocol frames 3.2.2 EPON link parameter statistics The three types of information that are the most critical for reflecting the performance of EPON links: the error rate of the EPON preamble CRC8 check, the FCS check error rate of each LLID corresponding frame, and each LLID Corresponding traffic flow information is reported.

Based on the user's concern about several types of statistical data, the bottom layer supports the control of the enabling and reporting of various types of statistics. At the arrival of the reporting period, statistical information will be packaged and output. In order to still be able to make statistics when the data is output, we use two sets of statistics modules. When one set of statistics needs to be output, it switches to another set of parameters for statistics.

In EPON, OAM messages are all carried in the format of TLV (Type Length Value) and then encapsulated into the data field in the OAM frame. This format makes OAM messages very extensible. Here we refer to the encapsulation method of the EPNOAM frame. Statistical data will be encapsulated into a TLV first. The type field in the TLV header indicates which type of statistical information the TLV carries, and the length of the TLV is indicated by the length field. When encapsulating a TLV into an Ethernet frame, the subtype field is still used to identify the payload portion of the Ethernet frame as statistical information, and the flag field is reserved. The encapsulation format is shown in Figure 6.

Figure 6: Encapsulation format of statistical information 3.2.3 Configuration Resolution Various configuration messages from the software console are processed by the configuration resolution module and sent to the corresponding module. The user configurable content includes the filter condition of the EPON protocol frame, the enabling and reporting period of each link statistic item, and the DA/SA/type field when the data is encapsulated into an Ethernet frame.

Taking into account the reliability of the communication line with the software console, when the configuration resolution module receives a configuration message without error, it will generate a confirmation frame containing the configuration message number and the configuration effective time to inform the console, format and statistics. Frames are similar.

3.2.4 Output Control It schedules the collected uplink and downlink EPON protocol frames, statistical information frames, and configuration confirmation frames to the external SRAM, and then controls them to output to the 100Mbit ports. This reads and writes to the external SRAM. to fulfill.

External memory We use the pipelined type Zero Bus Shift (ZBT) SRAM, which does not require any wait cycles for the read and write operations, and thus the bus utilization can reach 100%. The data interface width of the SRAM is 36 bits, and each data bit width to be written into the SRAM is 9 bits (8 bit data + 1 bit frame envelope information), so that each path data writes 36 bits wide data to the SRAM once every 4 clocks. Wire-speed storage can be achieved. For this purpose, the SRAM is divided into three independent memory areas, and the read and write time slots are allocated as follows: The first clock cycle can write the EPON uplink protocol frame to the memory area 1 of the SRAM, and the second clock cycle can be stored in the SRAM. The second zone writes the EPON downlink protocol frame. The third clock cycle can write statistics information frames and configuration confirmation frames to the SRAM memory area 3, and the fourth clock cycle can read data from the SRAM and read the complete one from a block of memory area. After the frame is switched to reading another block of memory.

3.3 Test Results We conducted actual tests on the EPON system of Beijing Greenwell Technology Development Co., Ltd. The developed EPON tester can extract all the frames involved in the ONU registration process; when receiving the filter conditions configured by the console, it will return a confirmation message to the console, and then extract specific MPCP/OAM according to the configured filtering conditions. Frames; Statistics of some or all of several types of link parameters can be collected, and the reporting period of each type of statistical data can be independently configured. All data sent to the console is encapsulated into Ethernet frames according to the set format. In addition, we also tested the parameters supported by the EPON tester hardware platform. The test results show that all functions and performance indicators are in accordance with the design requirements.

4. Conclusion This article explained the significance of researching and developing the EPON tester, briefly described its functional structure, and emphatically elaborated the FPGA design and implementation of its hardware platform. EPON tester can effectively help network operators conduct equipment interoperability testing, project acceptance and network operation and maintenance.